On-chip interconnects, such as wires, are used to connect different parts of an integrated circuit together. The delay of a wire is approximately equal to Rwire*Cwire*L2 (where Rwire is the resistance of the wire per unit length, Cwire is the capacitance per unit length, and L is the length of the wire). From this equation it can be seen that, as the length of a wire decreases, the delay of the wire also decreases. Therefore, the latency of a wire decreases along with feature size scaling. The delays associated with gates also decrease with feature size scaling. However, because the gate delays are shrinking faster than the interconnect delays, the relative delay of interconnects to gates is increasing with feature size scaling. The delay per unit length of interconnects relative to gate delays approximately doubles every technology generation.
One way to reduce the delay of a wire is to break it into multiple smaller segments using buffers or repeaters. This makes the delay of the wire grow linearly with the number of segments. Wider wires can also be used to improve overall delay, because they require a fewer numbers of repeaters. However, wider wires also require more energy per bit to drive because of their larger capacitance, and they take up a greater amount of space on an integrated circuit.
For example, optimally repeated copper wires of typically minimum width and spacing deliver a relatively constant delay per unit length, increasing from 55 ps/mm for 0.18 μm technology to approximately 80 ps/mm in 35 nm technology. However, when measured proportionally to gate delay, this delay per mm increases dramatically from 1 FO4 (fanout of 4) gate delay in a 0.18 μm technology to 7 FO4 gate delays in a 35 nm technology. This shows that, although wires may have a relatively constant delay per unit length, when compared to decreasing gate delays, the relative delay of interconnect is actually increasing.